One type of prior nonvolatile computer memory is the flash electrically erasable and programmable read-only memory ("flash EPROM"). The flash EPROM can be programmed by a user, and once programmed, the flash EPROM retains its data until erased. Once programmed, the entire contents of the flash EPROM can be erased by electrical erasure in one relatively rapid operation. The flash EPROM may then be reprogrammed with new data.
One prior use of flash EPROMs is in microprocessor-based systems as in-system reprogrammable nonvolatile storage means. Given that flash EPROMs are electrically erasable and programmable, flash EPROMs typically offer cost-effective means for storing and updating programs. A central processing unit ("CPU") can reprogram a flash EPROM and this reprogramming is referred to as in-system writing ("ISW"). With ISW, the CPU controls the reprogramming of the flash EPROM and the programming voltage V.sub.PP is generated locally within the system.
FIG. 1 illustrates in block diagram one prior microprocessor system 10 with ISW capability. System 10 includes a CPU 1 that controls the reprogramming of flash EPROM 3. A communication port 6 links microprocessor system 10 to a host computer (not shown) via bus 4. The host computer contains the code and data that is to be programmed into flash EPROM 3. The code and data is supplied to CPU 1 via communication port 6.
Microprocessor system 10 also includes a boot memory 2 that stores (1) CPU boot code for system initialization, (2) communication software, and (3) reprogramming algorithms for ISW of flash EPROM 3. The boot code includes I/O drivers, ASCII to binary conversion tables, and routines for hardware initialization. Boot memory 2 is any type of nonvolatile memory device, such as a ROM or an EPROM erasable with ultraviolet light.
Prior microprocessor system 10 also typically includes RAM 7 and V.sub.PP generator 5. RAM 7 is used for storing code and data that changes. V.sub.PP generator 5 supplies the program/erase voltage V.sub.PP for the reprogramming of flash EPROM 3. V.sub.PP is typically about 12 volts.
One disadvantage of system 10 is that flash EPROM 3 cannot be read while it is being programmed or reprogrammed. Thus, CPU 1 is typically idle while flash EPROM 3 is being programmed The erasure of flash EPROM 3 typically takes about 0.5 to 30 seconds. The programming of a byte of a flash EPROM 3 typically takes about 16 to 400 microseconds. The programming time of a flash EPROM 3 depends upon the size of the memory array of flash EPROM 3.
To erase flash EPROM 3, CPU 1 sends an erasure command to a command register of flash EPROM 3. CPU 1 then sends an erase verify command to flash EPROM 3 to stop erasure and start erase verification.
To program flash EPROM 3, CPU 1 sends a program command to a command register of flash EPROM 3. An address and data are then latched into flash EPROM 3 and programming starts. CPU 1 then sends a program verify command to flash EPROM 3 to terminate programming and program verification.
Another disadvantage associated with prior system 10 is its hardware requirements. System 10 typically requires nonvolatile boot memory 2 to store the boot code and reprogramming algorithms. System 10 also typically requires RAM 7. Boot memory 2 and RAM 7 each have associated peripheral circuitry. That peripheral circuitry typically includes decoders, address latches, and input/output buffers.
One prior approach to solving this problem is to store boot information in a boot area is flash EPROM 3 and eliminate boot memory 2. When flash EPROM 3 is to be written to (i.e., reprogrammed), CPU 1 first loads the reprogramming algorithms and the communication software from the boot area of flash EPROM 3 into RAM 7. CPU then executes the reprogramming algorithms stored in RAM 7 and thus carries out the ISW reprogramming of flash EPROM 3.
One disadvantage of this prior approach is that the boot information takes up portions of both RAM 7 and flash EPROM 3. Depending upon the system requirements, this may require a larger RAM 7. Another disadvantage of this prior approach is that it requires extra CPU time for ISW. That extra time includes the time it takes to load RAM 7 with the boot information.